1. Field of the Invention
This invention relates to frequency dividers and dual-modulus prescalers.
2. Description of the Related Art
Indirect phase-locked frequency synthesizers, commonly known as phase-locked loops (PLLs), are often used to generate a signal at a desired frequency. A block diagram of a typical PLL 10 is shown in FIG. 1. The illustrated PLL 10 includes a voltage-controlled oscillator (VCO) 18, a feedback division network 20, a reference divider 12, a phase detector 14, and a loop filter 16.
The output signal 19 of the VCO 18 is divided within the feedback division network 20. The reference signal 11, typically generated by a crystal oscillator, is divided within the reference divider 12. The output 21 of the feedback division network 20 and the output 13 of the reference divider 12 are then compared within the phase detector 14. Any phase difference between the two signals results in the phase detector 14 generating a corresponding error correction signal 15. This error correction signal 15 is filtered by the loop filter 16 and applied to the VCO 18, causing the output signal 19 of the VCO 18 to change so that the phase difference between the divided reference signal 13 and divided output signal 21 will be reduced.
A common method of changing the frequency of the VCO 18 involves controlling the feedback division value N. Typically, the reference division value, R, is a constant and thus the phase detection frequency, FCR, is also a constant. The amount of time between when N is changed and when the VCO's frequency has settled to within some specified error of the desired frequency (commonly called settling time) is inversely proportional to FCR because an inversely proportional relationship exists between settling time and the closed loop bandwidth of the PLL 10. In order to maintain a stable loop, the closed loop bandwidth must be restricted to be a small percentage of FCR, typically 10% or less. Additionally, the phase noise level of the PLL 10 inside its closed loop bandwidth is inversely proportional to FCR, because the phase noise level of the PLL inside its closed loop bandwidth is directly proportional to the magnitude of N, and an inversely proportional relationship exists between the magnitudes of N and FCR. Conversely, the frequency resolution of the PLL is directly proportional to FCR because the frequency resolution of the PLL is equal to the product of FCR and the resolution in changing the value of N.
Two common implementations of a variable feedback division network 20 have evolved in attempts to provide fast settling time, fine frequency resolution, and low integrated phase noise. A block diagram of one implementation, included in an integer-N PLL 10, is shown in FIG. 2. The feedback division network 20 of an integer-N PLL typically includes a dual-modulus (P/{P+U}) prescaler 26 followed by a main (M) counter 22 and an auxiliary (A) counter 24. The M counter 22 and the A counter 24 are typically implemented as integer down-counters. The output 25 of the dual-modulus prescaler 26 is applied as a clock signal to both the M and A counters, and thus both devices count downwards simultaneously from their programmed initial count values.
The programming of the M and A counters is such that the value of M is always greater than the value of A, ensuring that the A counter 24 reaches its terminal count of zero before the M counter 22 reaches its terminal count of zero. When the A counter 24 reaches its terminal count of zero, its modulus control output 23 (MC) toggles state. Once MC toggles, the A counter 24 ceases to count further until the M counter 22 reaches its terminal count of zero. However, the M counter 22 (which at that point in time contains a count value of {M−A}) continues counting downwards until it reaches its terminal count of zero. At this time, the M counter 22 outputs a pulse to the phase detector 14, and both the M and A counters re-load their programmed initial count values and the process starts over again.
The dual-modulus prescaler 26 is initially configured such that it divides by the alternate {P+U} integer modulus. The toggled state of MC causes the dual-modulus prescaler 26 to divide by the primary (P) integer modulus.
This integer-N implementation yields an integer value for the feedback division value N and provides integer resolution when changing the value of N. Because the resolution in changing the value of the feedback division is just U, the difference in value between the prescaler's moduli, U is typically set to one (1). In order to change the VCO's frequency by small steps, the integer-N implementation is forced to make the phase detection frequency, FCR, equal to the step size divided by U, the resolution in changing the value of N. For closely spaced channels (small frequency steps), this leads to a large integer feedback division value, N, which increases the phase noise level inside the closed loop bandwidth, and slows settling time due to the narrow closed loop bandwidth limitation imposed by the small phase detection frequency. Due to these performance limitations, the integer-N implementation often results in a sub-optimal PLL.
The integer-N implementation is described by the following equations where A, M, R, P, & U are all integers:FCR=FREF÷R  (1)FCV=FOUT÷NINT=FCR  (2)NINT=A*(P+U)+(M−A)*P=M*P+A*U  (3) FOUT=NINT*FCR=(M*P+A*U)*FCR=[(M*P+A*U)÷R]*FREF  (4)
FIG. 3 shows a block diagram of a second implementation of a feedback division network 20 with variable division, which is included in a typical fractional-N PLL. Feedback division networks in fractional-N PLLs typically include a divider 28 that is modulated between two different integer division values such that the time averaged division value becomes a fractional value determined by the duty cycle at each integer divisor.
The arithmetic unit 30 that controls the divider modulus is typically an accumulator-based circuit that dynamically switches its modulus control output 23 in such a way as to cause the feedback division value, N, to be a time-averaged division value that is a fractional number between the integers D and {D+E}. This time-averaging is completed across F cycles of the phase detection frequency, FCR, such that in K out of the F cycles, the integer divider modulus {D+E} is used, while in the remaining {F−K} cycles, the integer divider modulus D is used.
This fractional-N implementation yields a fractional value for the feedback division value N on a time-averaged basis, but the instantaneous feedback division value during any given cycle of the phase detection frequency is still an integer value (either D or {D+E}). The fractional-N implementation also yields a fractional resolution in changing the value of N as determined by the integers E, F, and K. The fractional-N implementation is described by the following equations where D, E, F, K, & R are all integers:FCR=FREF÷R  (5)FCV=FOUT÷NFRAC=FCR  (6) NFRAC=[K*(D+E)+(F−K)*D]÷F=D+(E*K÷F)  (7)FOUT=NFRAC*FCR=[D+(E*K÷F)]*FCR={[D+(E*K÷F)]÷R}*FREF  (8)
In the locked condition, during {F−1} out of the F cycles of the phase detection frequency, the phase detector 14 detects a systematic phase error caused by the action of the arithmetic unit 30 and produces corresponding error correction signals 15. These systematic corrections give rise to spurious signals in the VCO's output unless the frequency content of the error correction signal 15 is adequately filtered by the loop filter 16.
The fractional-N implementation allows the phase detection frequency, FCR, to be increased without a loss of frequency resolution because of the increased resolution in controlling the feedback division value N. The increase in FCR allows faster settling times due to the allowable increase in closed loop bandwidths. However, increased closed loop bandwidths provide less filtering of the spurious frequency content on the error correction signal 15. The increase in FCR also allows lower phase noise levels inside the closed loop bandwidth due to the reduction in the magnitude of N. These benefits come at the expense of the presence of spurious signals in the VCO output 19 or the expense of additional special circuitry within the arithmetic unit 30 used to alter the modulus control signal 23 in such a way that the resultant error correction signals 15 could be adequately filtered by the loop filter 16. Due to these performance and hardware limitations, the fractional-N implementation often results in a sub-optimal PLL.